To design and implement 3 X 8 decoder and 8 X 3 encoder circuit using Verilog HDL and verify its truth table ... The output lines define the 2N-bit code for the binary information. A 3 to 8 decoder ...

The testbench instantiates the Behavioral model ... granting request 8, and then changes again to 00001000, granting request 4 again, thus moving in round robin fashion, skipping any inactive request.