- In Cadence Simulated a Low Power and High-Performance Line Decoder Circuit \\ - Used Transmission Gate Logic (TGL) or Differential Pass Transistor Logic (DVL) gates for compact design \\ - For ...

The Verilog (.v) file above has the primary code for the working of the SRAM Cell and a testbench to test the simulation This project was initially created as a schematic using Cadence Virtuoso. SRAM ...