Figure 1 shows the typical block diagram of a Structured ASIC. Structured ASICs can include embedded CPUs and DSPs, ... Figure 3 shows a typical design flow for the LSI Rapid Chip product.

Paul Taubman is a senior design engineer for Tality Corp., Cadence Design Systems' services organization. In this article he shows how test engineers should interact with designers in order to ...

The problem for Infrant Technologies, a young network storage IC company, was to figure out how to avoid the typical iterative design scenario. For our latest design, a 250-MHz network storage device ...

The ASIC design flow, when viewed in a linear progression, hides the required interaction of processes (see Figure 1, below). ... Prior to the start of most logic designs, a general block diagram is ...

So we adopted an ASIC design flow that was based on Magma's integrated RTL-to-GDSII system. We would use Blast Create to synthesize the design and then hand off the netlist to our ASIC vendor to ...