In VLSI systems design, reversible Logic has gained importance for Reducing power. This paper focuses on designing of sequential circuits and reducing the number of constant inputs - CI and the ...

The Verilog coding of these multipliers using a full adder module made up of reversible logic has been done on Xilinx 14.6 ISE and implemented on SPARTAN 6 FPGA. Keywords: Reversible logic, Peres gate ...