To design and implement 3 X 8 decoder and 8 X 3 encoder circuit using Verilog HDL and verify its truth table. The combinational circuit ... Generate the RTL schematic and save the logic diagram.

This lab consists of 6 parts: Please describe a simple digital circuit from AND, OR and NOT gate primitives using VHDL, and verify its correctness in simulation using waveforms (i.e. compare ...