Sythesizable, modular Verilog implementation of 802.11 OFDM decoder optimized for meta data generation. - sharjeel778866/openofdm_vivado_2019 ...

High-level synthesis (HLS) tools significantly accelerate the hardware design process by using software programming languages such as C/C++. Well optimized code can be synthesized by the HLS tools ...

This paper presents the design and implementation of a 128-bit Asynchronous Gray Code FIFO using Verilog HDL. The FIFO is designed for bidirectional transfer of data between different clock domains ...