The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static ...

In this thesis, 8-bit SAR ADC firstly designed in 90nm technology and comparing power consumption and delay with 45nm technology. Schematics designed using Cadence Virtuoso Tool ... This allowed for a ...