News

IEEE1y
Design of full subtractor using DPL logic and MTCMOS technique to reduce the leakage current and area
The full subtractor design using DPL logic and MTCMOS technique is proposed in this paper. The application of combinational logic circuit is numerous in Digital Signal processing, microprocessors and ...
GitHub1y
uksamarth/Full-Subtractor-CMOS-circuit-design-in-Cadance: This is the CMOS VLSI course project on Full Subtractor done using Cadance software. - GitHub
The corresponding maps for logic functions for outputs of the full subtractor namely difference and borrow. This repository provides the schematic, layout, and simulation files for the Full Subtractor ...
GitHub15d
darshan0309/CS220-MIPS-Processor - GitHub
Full Subtractor Architecture: Created a full subtractor using AND, OR, XOR, and NOT gates in a structural style to connect components for bit subtraction with a borrow. 32-bit Subtractor: Instantiated ...