This report discusses our project’s design to speed up Dijkstra’s shortest path finding algorithm on FPGA (for the purpose of this project we’ll be using Altera’s Cyclone V board). Parallel ...

algorithm. Results indicates that the FTS FPGA implementation requires less number of gates than FS and the required number of cycles needed to complete motion search for one block is much lower. This ...

Wear-leveling algorithm research become one of the most important topics of PCRAM application. FPGA based MMU implementation is a bridge to connect IoT terminal MCU with PCRAM. Usage index based block ...