This repository contains Verilog code for a 2x1 Multiplexer (MUX) implemented in three distinct styles: Conditional, Dataflow, and Gate-Level. A comprehensive testbench is included to verify the ...

Description A 2-bit full adder and test bench using Verilog.The 2-bit adder is consisted of 2 1-bit adder using structural modeling. The first adder ultizes "and" and "or" gates while the second adder ...