This paper proposes comparator circuits that use static logic circuits and thus require no static current and no static (DC) power. HSPICE simulations of these circuits using model ... technology and ...

CMOS Layout Design for Combinational Circuits, using the Micorwind layout design software The layouts are optimized to enhance the performance and efficiency of the circuits. 4-bit adder subtractor ...

at Shahid Beheshti University in Iran, demonstrate a comparator-based buffer circuit using a variable ... switched-capacitor circuits for scaled CMOS technologies, IEEE J. Solid-ST. Circ., 41 (2006), ...

Therefore, we call our PTL circuits CMOS-based CNT–PTL circuits. The main benefit of using the CMOS-based PTL circuits is that the number of transistors can be greatly reduced when compared with ...

This paper proposes comparator circuits that use static logic circuits and thus require no static current and no static (DC) power. HSPICE simulations of these circuits using model ... technology and ...