Abstract: A new algorithm called "path limited PRML" is described which has been used to implement a high speed Viterbi decoder LSI. Furthermore, this LSI has been used to realize an experimental 1/2" ...

The study involves the implementation of various reversible Arithmetic Logic units using Verilog in Vivado ML Edition – 2023.2 for FPGA, targeting the Zynq-7000 family of FPGAs.