This paper presents an efficient way to realize a reversible n-bit subtractor circuit incorporating a reversible full adder based on 2's Complement computation. We propose a reversible controlled ...

This Verilog module implements a 4-bit Adder-Subtractor circuit, ... Subtraction: a - b (e.g., 4'b1010 - 4'b0011). Handles overflow and borrow detection. Example Test Cases a b mode sum cout 4'b0110 4 ...

Implementation of an arithmetic logic unit for complex operation. The current design is able to handle addition, subtraction, multiplication and division of the complex numbers. - ...

In parallel, investigations into the design of reversible ternary full-adder/full-subtractor circuits have reported promising reductions in quantum cost and energy dissipation, emphasising the ...