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IEEE20d
A 3.25Gb/s, 13.2pJ/b, 0.64mm<sup>2</sup> Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS - IEEE Xplore
A 0.64mm2 configurable successive-cancellation list polar decoder is designed in 40nm CMOS for 5G wireless applications. The decoding tree is split to 4 subtrees to be decoded by 4 sub-decoders in ...
IEEE25d
An architecture and implementation of MPEG audio layer III decoder using dual-core DSP - IEEE Xplore
A new architecture for the MP3 decoding system is proposed and implemented. The proposed system is based on a processor employing a dual-core (DSP and RISC) architecture. The MP3 decoding algorithm is ...