PIPE, which stands for the Physical Interface for PCI Express Specification developed by Intel, has the stated intent of providing a standard interface between the internal logic of a PCI Express design and the analog and high-speed circuitry required to implement the serial link.
PCI Express* Architecture - Intel
The PHY Interface for the PCI Express* (PIPE) Architecture Revision 7.0 is an updated version of the PIPE spec that supports PCI Express*, SATA, USB3.2, DisplayPort, and USB4 Architectures.
[转载]PCIe扫盲——PCI Express物理层接口（PIPE） - 知乎专栏
PCIe物理层接口（Physical Interface for PCI Express，PIPE）定义了 物理层 中的， 媒介层 （Media Access Layer，MAC） 和物理编码子层 （Physical Coding Sub-layer，PCS） 之间的统一接口，旨在为提供一种统一的行业标准。 如下图所示： 其中MAC和PCS都属于PCIe中的 物理层逻辑子层部分，而 PMA （Physical Media Attachment Layer）则属于物理层电气子层。 需要注意的是， PIPE规范是由Intel提出的行业建议，并非PCI-SIG规定的PCIe标准之一。 PCIe设备厂 …
Demystifying PCIe PIPE 5.1 SerDes Architecture - Synopsys
Nov 20, 2019 · Explore the complexities of PCIe PIPE 5.1 SerDes Architecture with our in-depth analysis, helping you demystify its design and functionality.
2.5.1. PCI Express (PIPE) - Intel
PCI Express (PIPE) You can use Stratix® 10 transceivers to implement a complete PCI Express solution for Gen1, Gen2, and Gen3, at datarates of 2.5, 5.0, and 8 Gbps, respectively. To implement PCI Express, you must select the external oscillator as …
PHY Interface for PCI Express* and SATA* Specification V4.3
The PHY Interface for the PCI Express*, SATA*, and USB* Architectures (PIPE) is intended to enable the development of functionally equivalent PCI Express, SATA and USB PHY's. Such PHY's can be delivered as discrete IC's or as macrocells for inclusion in ASIC designs.
PIPE 5.1.1 for PCIe 5.0, DP 1.4, USB 3.2, SATA - Synopsys
Oct 24, 2018 · To accelerate PCIe system development, PIPE interface is widely being used in the industry. With the base specification graduating to 5.0, PIPE specification is also catching up and has advanced to version 5.1.1.
The Advantages of the PCIe SerDes Architecture and its …
Oct 20, 2020 · The PCIe PIPE 5.1 SerDes Architecture, in which the PIPE stands for PHY Interface for the PCI Express, is a necessary evolution to match the latest specifications. However, it not only meets the latest specifications, but it also permits scaling for protocol developments in the future.
Demystifying PCIe PIPE 5.1 SerDes Architecture - Design And Reuse
Nov 25, 2019 · SerDes architecture for PIPE interface achieves scalability by introducing several key changes to the responsibilities of the Physical Coding Sublayer (PCS) and Media Access Layer (MAC), along with updates to the signaling interface.
PCI Express PIPE interface functional coverage - VerifSudha
Oct 9, 2017 · What started off, as “PHY Interface for the PCI Express Architecture” was soon promoted to “PHY interface for the PCI Express, SATA and USB3.1 and SATA”. It was primarily designed to ease the integration of digital MAC Layer with the mixed signal PHY.